1 publication order number : NDBA100N10B/d www.onsemi.com ? semiconductor component s industries, llc, 2015 march 2015 - rev. 1 ordering information see detailed ordering and shipping info rmation on page 5 of this data sheet. NDBA100N10B features ? low on-resistance ? low gate charge ? high speed switching ? 100% avalanche tested ? pb-free, halogen free and rohs compliance specifications absolute maximum ratings at ta = 25 c parameter symbol value unit drain to source voltage v dss 100 v gate to source voltage v gss 20 v drain current (dc) i d 100 a drain current (pulse) pw 10 s, duty cycle 1% i dp 400 a power dissipation tc=25 c p d 110 w junction temperature tj 175 c storage temperature tstg ? 55 to +175 c source current (body diode) i s 100 a avalanche energy (single pulse) * 1 e as 147 mj lead temperature for soldering purposes, 3mm from case for 10 seconds t l 260 c thermal resistance ratings parameter symbol value unit junction to case steady state r jc 1.36 c/w junction to ambient * 2 r ja 62.5 note : * 1 v dd =48v, l=100 h, i av =40a (fig.1) * 2 surface mounted on fr4 board using recommended footprint power mosfet 100v, 6.9m ? , 100a, n-channel electrical connection n-channel stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. v dss r ds (on) max i d max 100v 6.9 m ? @15v 100a 8.2 m ? @10v 100n10 b lot no. tl packing type : tl marking to-263 case 418aj 4 1 2 3 1 3 2, 4 1:gate 2 : drain 3:source 4 : drain
NDBA100N10B www.onsemi.com 2 electrical characteristics at ta = 25 c parameter symbol conditions value unit min typ max drain to source breakdown voltage v( br ) dss i d =10ma, v gs =0v 100 v zero-gate voltage drain current i dss v ds =100v, v gs =0v 10 a gate to source leakage current i gss v gs = 20v, v ds =0v 100 na gate threshold voltage v gs (th) v ds =10v, i d =1ma 2 4 v forward transconductance g fs v ds =10v, i d =50a 75 s static drain to source on-state resistance r ds (on)1 i d =50a, v gs =15v 5.7 6.9 m r ds (on)2 i d =50a, v gs =10v 6.3 8.2 m input capacitance ciss v ds =50v, f=1mhz 2,950 pf output capacitance coss 1,250 pf reverse transfer capacitance crss 20 pf turn-on delay time t d (on) see fig.2 40 ns rise time t r 385 ns turn-off delay time t d (off) 68 ns fall time t f 52 ns total gate charge qg v ds =48v, v gs =10v, i d =100a 35 nc gate to source charge qgs 13 nc gate to drain ?miller? charge qgd 10 nc forward diode voltage v sd i s =100a, v gs =0v 1.1 1.5 v reverse recovery time t rr see fig.3 i s =100a, v gs =0v, v dd =50v, di/dt=100a/ s 130 ns reverse recovery charge q rr 400 nc fig.1 unclamped inductive switching test circuit fig.2 switching time test circuit fig.3 reverse recovery time test circuit product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions. NDBA100N10B 50 50 v dd l 10v 0v g s d v dd NDBA100N10B l driver mosfet g s d
NDBA100N10B www.onsemi.com 3
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NDBA100N10B www.onsemi.com 5 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidiaries in the united st ates and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a lis ting of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf . scillc reserves the right to make changes with out further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specific ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated fo r each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc pro ducts are not designed, intended, or authorized for use as com ponents in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees ar ising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that sci llc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject t oall applicable copyright laws and is not for resale in any manner. package dimensions NDBA100N10Bt4h d 2 pak-3 (to-263, 3-lead) case 418aj issue b ordering information device package shipping note NDBA100N10Bt4h d 2 pak-3 (to-263, 3-lead) 800 pcs. / tape & reel pb-free and halogen free ? for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. http://www .onsemi.com/pub_link/co llateral/brd8011-d.pdf note on usage : since the NDBA100N10B is a mosfet product, please avoid using this de vice in the vicinity of highly charged objects. dim min max min max millimeters inches d e a 0.160 0.000 0.020 0.012 0.045 0.330 0.260 0.380 0.245 0.575 0.070 ----- ----- 0o 0.190 0.010 0.039 0.029 0.065 0.380 ----- 0.420 ----- 0.625 0.110 0.066 0.070 8o 4.06 0.00 0.51 0.30 1.14 8.38 6.60 9.65 6.22 14.60 1.78 ----- ----- 0o 4.83 0.25 0.99 0.74 1.65 9.65 ----- 10.67 ----- 15.88 2.79 1.68 1.78 8o b c2 e 0.100 bsc 2.54 bsc a1 c l h l2 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. chamfer optional 4. dimensions d and e do not include mold flash. mold flash shall not exceed 0.005 per side. these dimensions are measured at the outermost extremes of the plastic body at datum h. 5. thermal pad contour is optional within dimensions e, l1, d1 and e1. 6. optional mold feature e1 l1 d1 l3 0.010 bsc 0.25 bsc m e d h l1 b e a1 b h l m detail c seating plane a 2x m a m 0.10 b c2 c a b seating plane detail c view a-a side view top view e2 l2 a a view a-a e1 d1 l1 optional constructions l3 gauge plane note 3 m a m 0.10 b xx xxxxxxxxx awlywwg generic marking diagrams* a = assembly location wl = wafer lot y=year ww = work week w = week code (ssg) m=monthcode(ssg) g=pb-freepackage aka = polarity indicator xxxxxxxxg ayww *this information is generic. please refer to device data sheet for actual part marking. pb ?free indicator, g or microdot , may or may not be present. ayww xxxxxxxxg aka *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 0.366 0.100 dimensions: inches pitch 2x 0.653 0.063 2x 0.436 0.169 soldering footprint* note 6 xxxxxx xxymw
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